The type bit and byte have also been created that can only hold 2 states 0 or 1 no x or z. Using these types offers a small speed improvement but I would recommend not using them in RTL as your verification may miss uninitialized values or critical resets.
The usage of bit and byte would be more common in testbench components, but can lead to issues in case of having to drive x's to stimulate data corruption and recovery. At the time of writing I was under the impression that logic could not be used for tristate, I am unable to find the original paper that I based this on. Until further updates, comments or edits, I revoke my assertion that logic can not be used to create tri-state lines.
The tri type has been added, for explicitly defining a tri-state line. It is based on the properties of a wire , logic is based on the properties of a reg. If you no longer have to support backwards compatibility Verilog then I would recommend switching to using logic and tri.
Using logic aids re-factoring and and tri reflects the design intent of a tristate line. The choice of the name reg turned out to be a mistake , because the existence of registers is instead inferred based on how assignments are performed. Due to this, use of reg is essentially deprecated in favor of logic , which is actually the same type.
Practically speaking, for RTL it usually doesn't matter whether you declare with reg , or logic , or wire. However, if you have to make an explicit declaration of a 4-state type as opposed to when you don't , you should typically choose logic since that is what is intended by the language.
These data types appear inside the always or initial blocks and store values i. I agree that they can behave identical as Morgan mentioned, but they can be imagined as a piece of hard wire, the value of which changes only the value at the other end or the source changes. Logic data type doesn't permit multiple driver. The last assignment wins in case of multiple assignment.
Logic data type simply assign the last assignment value. Stack Overflow for Teams — Collaborate and share knowledge with a private group. Create a free Team What is Teams? Collectives on Stack Overflow. Learn more. Difference of SystemVerilog data types reg, logic, bit Ask Question.
Search only containers. Search titles only. Search Advanced search…. New posts. Search forums. Log in. Install the app. Contact us. Close Menu. Welcome to EDAboard. To participate you need to register. Registration is free. Click here to register now. Register Log in. JavaScript is disabled. When I first wondered why it was possible to always write RTL using SystemVerilog logic keyword, I never expected it to become a major undertaking that involved reading and interpreting two different specifications, understanding complex language rules, and figuring out their nuances.
At least I can say that the recommendations are easy to remember. I hope this article gives you a good summary of Verilog reg , Verilog wire , SystemVerilog logic , their history, and a useful set of recommendations for RTL coding.
I do not claim to be a Verilog or SystemVerilog language expert, so please do correct me if you felt I misinterpreted anything in the specifications. The accompanying source code for this article is a SystemVerilog design and testbench toy example that demonstrates the difference between using Verilog reg, Verilog wire, and SystemVerilog logic to code design modules.
Download the code to see how it works! Good article. However, there is one significant gotcha that users need to be aware of. As a variable type, assigning a value to a logic variable as part of the declaration merely initializes it to that value. No continuous assignment is inferred. Thanks for pointing that out Evan! Like you said, the particular form of assignment in the first row of your example code is called net declaration assignment section The second line in your example is a variable declaration assignment section That is indeed a gotcha if one just replaced all instances of wire with logic.
Great comment! Hi Varun. Yes, the same rules would apply when using SystemVerilog logic. Hi Shaily. Thanks for your comment. Are vddmp and gndmp functional signals? Or are they power supplies? Is it allowed to induce a latch or flip-flop inside the combinational logic with some intentions?
Hi Jaehyuk. Thank you, Jason, for the article! One issue I see in replacing reg with logic is that it eliminates X from the variable. That way you may miss initialization problem. I think also using UPF will force X on the registers during power-down for verification.
I am not sure that with that practice it will be compatible with UPF. What do you think? Hi Dmitry. I have used logic variables successfully on projects that use all these methodologies. Notify me of follow-up comments by email. Notify me of new posts by email.
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